Level Shift Circuit and Semiconductor Integrated Circuit Including the Same

ABSTRACT

In a level shift circuit, including two Nch transistors Tn 1 , Tn 2  receiving a pair of complementary input signals and two Pch Transistors Tp 1 , Tp 2  of which gate terminals are cross-coupled to each other, nodes A and B as the drains of the two Nch transistors Tn 1 , Tn 2  operating in reverse to each other are connected together with a resistance Tp 3 . The resistance Tp 3 , constructed of a Pch transistor, is grounded at its gate to be in the normally ON state. For example, when the Nch transistors Tn 1  and Tn 2  go ON and OFF, respectively, a current initially flows from the high-potential node A through the resistance Tp 3  to the low-potential node B, raising the potential at the low-potential node B. Thus, the potential rise at the node B is sped up compared with the case that only the Pch transistor Tp 2  becoming ON contributes to the potential rise. This enables high-speed operation of the level shift circuit with a small number of elements.

TECHNICAL FIELD

The present invention relates to a level shift circuit required for asemiconductor integrated circuit having different power-supply voltages.

BACKGROUND ART

A conventional level shift circuit will be described.

FIG. 5 shows a conventional level shift circuit. Referring to FIG. 5,BUF1 denotes a buffer including inverters INV1, INV2 operating at a lowpower-supply voltage, BUF2 denotes a buffer including inverters INV3,INV4 operating at a high power-supply voltage, VDDH and VDDLrespectively denote a high-voltage power supply and a low-voltage powersupply, VSSH and VSSL respectively denote grounds (0V) for thehigh-voltage and low-voltage power supplies, Tn1 and Tn2 respectivelydenote first and second N-channel (Nch) MOS transistors, Tp1 and Tp2respectively denote first and second P-channel (Pch) MOS transistors, INdenotes an input signal terminal, OUT denotes an output signal terminal,A denotes a node to which the drain of the Nch MOS transistor Tn1, thedrain of the Pch MOS transistor Tp1 and the gate of the Pch MOStransistor Tp2 are connected, and B denotes a node to which the drain ofthe Nch MOS transistor Tn2, the drain of the Pch MOS transistor Tp2 andthe gate of the Pch MOS transistor Tp1 are connected.

The sources of the Nch MOS transistors Tn1, Tn2 and the sources of thePch MOS transistors Tp1, Tp2 are respectively connected to the groundVSSH for the high-voltage power supply and the high-voltage power supplyVDDH. The input signal terminal IN is for inputting a signal of a lowpower-supply voltage into the buffer BUF1. Signals in opposite phase toand in phase with the input signal IN from the two inverters INV1, INV2of the buffer BUF1 are input into the gates of the Nch MOS transistorsTn1, Tn2. The input of the buffer BUF2 on the output side is connectedto the node B, and the output thereof is connected to the output signalterminal OUT.

The operation of the conventional level shift circuit configured asdescribed above will be described.

When the input signal at the input signal terminal IN of the buffer BUF1has changed its level from low to high, signals in opposite phase to andin phase with the input signal are supplied from the inverters INV1,INV2 of the buffer BUF1 to the gates of the Nch MOS transistors Tn2,Tn1, respectively. At this time, the Nch MOS transistor Tn2, to the gateof which the signal in opposite phase to the input signal, that is, thesignal changing from high to low is applied, gradually increases its ONresistance, and this increases the drain-source voltage of the Nch MOStransistor Tn2. Roughly simultaneously with this, the Nch MOS transistorTn1, to the gate of which the signal in phase with the input signal isapplied, goes ON and gradually reduces its ON resistance, and thisreduces the drain-source voltage of the Nch MOS transistor Tn1.

With the operation of the two Nch MOS transistors Tn1, Tn2 describedabove, the gate voltage of the Pch MOS transistor Tp2 falls, and thusthe drain voltage thereof rises. This in return increases the gatevoltage of the Pch MOS transistor Tp1. Once the input signal input intothe buffer BUF1 finally reaches the high level, the drain-source of theNch MOS transistor Tn1 becomes completely conducting, and thus thevoltage of the node A becomes 0V. Also, the drain-source of the Nch MOStransistor Tn2 becomes completely non-conducting and the source-drain ofthe Pch MOS transistor Tp2 becomes conducting. Thus, the voltage of thenode B becomes equal to the high power supply voltage VDDH. At thistime, with the shift of the voltage of the node B to the highpower-supply voltage VDDH, the buffer BUF2, which operates at the highpower-supply voltage VDDH, shifts the potential of the output signal tobe output from the output signal terminal OUT to the high power-supplyvoltage VDDH, and supplies this output signal to a high power-supplyvoltage operating circuit not shown.

On the contrary, when the input signal at the input signal terminal INchanges its level from high to low, signals in opposite phase to and inphase with the input signal are supplied from the inverters INV1, INV2of the buffer BUF1 to the gates of the Nch MOS transistors Tn2, Tn1,respectively. At this time, the Nch MOS transistor Tn2, to the gate ofwhich the signal in opposite phase to the input signal, that is, thesignal changing from low to high is applied, goes ON and graduallyreduces its ON resistance, and this reduces its drain-source voltage.Roughly simultaneously with this, the Nch MOS transistor Tn1, to thegate of which the signal in phase with the input signal is applied,gradually increases its ON resistance, and this increases itsdrain-source voltage.

With the operation of the two Nch MOS transistors Tn1, Tn2 describedabove, the gate voltage of the Pch MOS transistor Tp1 falls and thus thedrain voltage thereof rises. This in turn increases the gate voltage ofthe Pch MOS transistor Tp2. Once the input signal input into the bufferBUF1 finally reaches the high level, the drain-source of the Nch MOStransistor Tn2 becomes completely conducting, and thus the voltage ofthe node B becomes 0V. At this time, with the shift of the voltage ofthe node B to 0V, the buffer BUF2, which operates at the highpower-supply voltage VDDH, shifts the potential of the output signal tobe output from the output signal terminal OUT to 0V, and supplies thisoutput signal to a high power-supply voltage operating circuit notshown. Also, the drain-source of the Nch MOS transistor Tn1 becomescompletely non-conducting and the source-drain of the Pch MOS transistorTp1 becomes conducting. Thus, the voltage of the node A becomes equal tothe high power-supply voltage VDDH.

As described above, with the conventional level shift circuit, it becamepossible to level-shift a signal output from a low power-supply voltageoperating circuit to a signal of the high power-supply voltage VDDH andoutput the level-shifted signal to a high power-supply voltage operatingcircuit.

However, the conventional configuration described above had thefollowing problem. When the input signal at the input signal terminal INchanges its level from high to low, for example, it takes one step forthe source-drain of the Nch MOS transistor Tn2 to become conducting tothereby reduce the potential of the node B. From this state, it takesone more step for the source-drain of the Pch MOS transistor Tp1 tobecome conducting to thereby change the potential of the node A from lowto high. That is, two steps are necessary until the potential states ofthe respective terminals of the Nch MOS transistors Tn1, Tn2 and the PchMOS transistors Tp1, Tp2 are changed and the output state, a high levelor a low level, is determined. This makes high-speed operationdifficult.

As a conventional level shift circuit intended to solve the aboveproblem, a level shift circuit disclosed in Patent Literature 1 is shownin FIG. 6. In the level shift circuit of FIG. 6, additional Nch MOStransistors Tn5, Tn4 are respectively connected in parallel with the twoPch MOS transistors Tp1, Tp2 of the level shift circuit shown in FIG. 5,and the complementary input signals from the buffer BUF1 are supplied tothe gates of the Nch MOS transistors Tn5, Tn4.

In the level shift circuit of FIG. 6 with the configuration describedabove, when the complementary input signals from the buffer BUF1operating at low power-supply voltage are reversed, one (for example,Tn1) of the pair of Nch MOS transistors Tn1, Tn2 is turned ON, changingthe node A to a low level. Simultaneously, one (for example, Tn5) of thetwo additional Nch MOS transistors Tn5, Tn4 is turned ON, changing thenode B to the high power-supply voltage VDDH. In this way, only one stepis necessary to raise the output state to a high level.

Patent Literature 1: Japanese Laid-Open Patent Publication No. 7-193488DISCLOSURE OF THE INVENTION Problems to be solved by the Invention

However, the conventional level shift circuit shown in FIG. 6 has aproblem that the area increases with the addition of the two Nch MOStransistors Tn5, Tn4. Moreover, with the drains of the Nch MOStransistors Tn5, Tn4 directly connected to the high-voltage power supplyVDDH, a reverse bias of the high power-supply voltage VDDH will beapplied to the back gates and drains of the Nch MOS transistors Tn5,Tn4, depending on the fabrication process of semiconductor elements.This may degrade the reliability of the elements.

Furthermore, in the conventional level shift circuit, the two Nch MOStransistors Tn5, Tn4 added for high-speed implementation must beoperated regardless of the frequency of the input signal IN. Therefore,if the input signal IN is low in frequency requiring no high-speed levelshift operation, power consumption will wastefully increase by theredundant operation of the Nch MOS transistors Tn5, Tn4.

In view of the technical problems described above, the first object ofthe present invention is achieving speedup of the operation of a levelshift circuit with a smaller number of elements than in the conventionalone while securing high level of reliability of the elements.

The second object of the present invention is achieving low powerconsumption by stopping the operation of added elements when low-speedlevel shift operation is enough.

Means for Solving the Problems

To attain the first object described above, the present invention adoptsa configuration that two nodes A and B are connected with each other viaa resistance in the conventional level shift circuit shown in FIG. 4.

To attain the second object described above, the present inventionadopts a configuration that the above additional resistance is composedof one normally ON transistor and this transistor is turned OFF asrequired.

Specifically, the level shift circuit of the present invention includes:first and second P-channel transistors of which sources are connected toa high-voltage power supply; and first and second N-channel transistorsof which sources are grounded, wherein complementary input signals inphase with and in opposite phase to an input signal from a lowpower-supply voltage operating circuit are respectively inputted togates of the first and second N-channel transistors, a drain of thefirst N-channel transistor is connected to a drain of the firstP-channel transistor and a gate of the second P-channel transistor, adrain of the second N-channel transistor is connected to a drain of thesecond P-channel transistor and a gate of the first P-channeltransistor, the level shift circuit further comprises a resistanceconnecting the drain of the first N-channel transistor with the drain ofthe second N-channel transistor, and the drain of the second N-channeltransistor serves as an output terminal to a high power-supply voltageoperating circuit.

In the level shift circuit described above, the resistance isconstructed of a P-channel transistor, and the P-channel transistor isgrounded at its gate, connected to the drain of the first N-channeltransistor at its source, and connected to the drain of the secondN-channel transistor at its drain, to be in the normally ON state.

In the level shift circuit described above, the resistance isconstructed of an N-channel transistor, and the N-channel transistor isconnected to a high-voltage power supply at its gate, connected to thedrain of the first N-channel transistor at its source, and connected tothe drain of the second N-channel transistor at its drain, to be in thenormally ON state.

In the level shift circuit described above, the resistance isconstructed of a P-channel transistor, and the P-channel transistorreceives an ON/OFF operation switch signal at its gate, connected to thedrain of the first N-channel transistor at its source, and connected tothe drain of the second N-channel transistor at its drain.

In the level shift circuit described above, the resistance isconstructed of an N-channel transistor, and the N-channel transistorreceives an ON/OFF operation switch signal at its gate, connected to thedrain of the first N-channel transistor at its source, and connected tothe drain of the second N-channel transistor at its drain.

In the level shift circuit described above, the ON/OFF operation switchsignal is an operation mode switch signal received from outside.

In the level shift circuit described above, the drains of the first andsecond N-channel transistors serve as differential output terminals forthe high power-supply voltage operating circuit.

The semiconductor integrated circuit of the present invention includesthe level shift circuit described above.

As described above, according to the present invention, in the case ofinput of a high-speed signal, when the input signal is reversed, acurrent is supplied from a node on the high potential side, out of nodesA, B on the low and high potential sides, to the node on the lowpotential side that is to shift to the high potential side through aresistance. This permits the node on the low potential side to raise itspotential swiftly to become high potential. Accordingly, the shift ofthe node on the low potential side to high potential can be sped up.Also, since the resistance provided additionally is a one-elementresistance made up of one transistor, the number of elements can bereduced by one compared with the conventional example shown in FIG. 5.Moreover, with one transistor as the resistance, no reverse bias of thehigh power-supply voltage will be applied between its back gate anddrain, and thus the reliability is highly secured.

In particular, according to the present invention, when a low-speedinput signal is input, one transistor constituting the resistance isturned OFF (non-conducting) to stop high-speed operation. This can saveredundant power consumption with the additional transistor (resistance)

EFFECT OF THE INVENTION

As described above, in the level shift circuit and the semiconductorintegrated circuit of the present invention, a current is supplied froma node on the high potential side to a node on the low potential sidethat is to shift to the high potential side through a resistance, tothereby enable speedup of the level shift circuit, while the resistanceis made up of one element and the element is prevented from beingexposed to a high power-supply voltage, to thereby highly secure itsreliability.

In particular, according to the level shift circuit of the presentinvention, when a low-speed input signal is input, the additionaltransistor (resistance) is turned OFF to thereby enable saving ofredundant power consumption of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a level shift circuit of Embodiment 1 of thepresent invention.

FIG. 2 is a view showing a level shift circuit of Embodiment 2 of thepresent invention.

FIG. 3 is a view showing a level shift circuit of Embodiment 3 of thepresent invention.

FIG. 4 is a view showing a level shift circuit of Embodiment 4 of thepresent invention.

FIG. 5 is a view showing a conventional level shift circuit.

FIG. 6 is a view showing a conventional level shift circuit improvedfrom the level shift circuit of FIG. 5.

DESCRIPTION OF REFERENCE NUMERALS

-   Tp1 First Pch MOS transistor-   Tp2 Second Pch MOS transistor-   Tn1 First Nch MOS transistor-   Tn2 Second Nch MOS transistor-   Tp3, Tp4 Pch MOS transistors (resistances)-   Tn3 Nch MOS transistor (resistance)-   Tn4 Nch MOS transistor-   Tn5 Nch MOS transistor-   BUF1, BUF2, BUF3 Buffers-   A, B Nodes-   IN Input terminal-   OUT Output terminal-   OUTP, OUTN Differential output terminals-   VDDH High power-supply voltage-   VDDL Low power-supply voltage-   VSSH Ground for high power-supply voltage-   VSSL Ground for low power-supply voltage-   Stb Standby mode signal    -   (ON/Off Switch Signal and Operation Mode Switch Signal)

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, level shift circuits of embodiments of the presentinvention will be described in detail with reference to the drawings.

Embodiment 1

FIG. 1 shows a configuration of a level shift circuit of Embodiment 1 ofthe present invention.

Referring to FIG. 1, BUF1 denotes a buffer on the input side includinginverters INV1, INV2 operating at a low power-supply voltage VDDL and aground (0V) VSSL for this voltage, and BUF2 denotes a buffer on theoutput side including inverters INV3, INV4 operating at a highpower-supply voltage VDDH. The buffers BUF1 and BUF2 should just have abuffer function, and are not necessarily a circuit having multi-stageconnection of inverters.

Also referring to FIG. 1, Tn1, Tn2 denote first and second Nch MOStransistors of which sources are connected to the ground (0V) VSSH forthe high-voltage power supply VDDH. Tp1, Tp2 denote first and second PchMOS transistors of which sources are connected to the high-voltage powersupply VDDH. IN denotes an input terminal for an input signal of a lowpower-supply voltage to be input into the buffer BUF1 on the input side(hereinafter, the input signal itself is also referred to as IN). Theinput signal IN is supplied from a low power-supply voltage operatingcircuit not shown.

The output of the first-stage inverter INV1 of the buffer BUF1 on theinput side, that is, a signal in opposite phase to the input signal INis input into the gate of the second Nch MOS transistor Tn2, while theoutput of the second-stage inverter INV2, that is, a signal in phasewith the input signal IN is input into the gate of the first Nch MOStransistor Tn1.

The drain of the Nch MOS transistor Tn1 is connected to the drain of thePch MOS transistor Tp1, and the connection point thereof is referred toas node A. The node A is connected to the gate of the Pch MOS transistorTp2. Likewise, the drain of the Nch MOS transistor Tn2 is connected tothe drain of the Pch MOS transistor Tp2, and the connection pointthereof is referred to as node B. The node B is connected to the gate ofthe Pch MOS transistor Tp1.

The first-stage inverter INV3 of the buffer BUF2 is connected to thenode B, and an output signal of the high power-supply voltage VDDH fromthe second-stage inverter INV4 is output externally from the outputterminal OUT (hereinafter, the output signal is also referred to asOUT).

The two nodes A and B are connected with each other via a Pch MOStransistor Tp3 as a resistance. Specifically, the Pch MOS transistor(resistance) Tp3 is connected to the node A at its source and to thenode B at its drain, and the ground VSSH for the high-voltage powersupply is connected to its gate, to allow for normally ON operation.

Hereinafter, the operation of the level shift circuit will be described.

When the input signal at the input signal terminal IN changes its levelfrom low to high, signals in opposite phase to and in phase with theinput signal are supplied from the two inverters INV1, INV2 of thebuffer BUF1, which is a low power-supply voltage operation circuit, tothe gates of the Nch MOS transistors Tn2, Tn1. At this time, the Nch MOStransistor Tn2, to the gate of which the signal in opposite phase to theinput signal IN, that is, a signal changing from high to low is applied,gradually increases its ON resistance. This increases the drain-sourcevoltage of the Nch MOS transistor Tn2, and thus the level of the node Bstarts to rise. Roughly simultaneously with this, the Nch MOS transistorTn1, to the gate of which the signal in phase with the input signal INis applied, starts going ON, allowing a current to start flowing fromthe node A to the ground VSSH through the Nch MOS transistor Tn1, andthus ON resistance of the Nch MOS transistor Tn1 gradually decreases.This reduces the drain-source voltage of the Nch MOS transistor Tn1, andthus lowers the level of the node A.

With the shift of the node A to the low level, the gate voltage of thePch MOS transistor Tp2 decreases, causing start of ON operation, andthus the drain voltage of the Pch MOS transistor Tp2, that is, the levelof the node B rises. The node B shifting to the high-level side was inthe low level before the change of the input signal IN, and the node Ashifting to the low-level side was in the high level before the changeof the input signal IN. Therefore, simultaneously with, or from thestage prior to, the start of the ON operation of the Pch MOS transistorTp2, a current flows from the node A on the high-level side to the nodeB on the low-level side through the resistance (Pch MOS transistor) Tp3,and this speeds up the potential rise at the node B shifting to thehigh-level side.

Thanks to the speedup of the potential rise at the node B shifting tothe high-level side, the time taken for the potential at the node B toexceed the threshold voltage of the first-stage inverter INV3 of thebuffer BUF2 on the output side operating at a high power-supply voltageis shortened, allowing the output from the output terminal OUT of thebuffer BUF2 to reach the high power-supply voltage VDDH early. With thepotential rise at the node B, also, the gate voltage of the Pch MOStransistor Tp1 rises. The Pch MOS transistor Tp1 therefore starts OFFoperation, making it difficult to supply the high power-supply voltageVDDH, and thus the level fall of the node A continues. Although the nodeB shifting to the high-level side is on the grounding route from thehigh-voltage power supply VDDH through the Pch MOS transistor Tp2, theresistance (Pch MOS transistor) Tp3 and the Nch MOS transistor Tn1 downto the ground, it is located upstream of the resistance (Pch MOStransistor) Tp3. Therefore, by appropriately setting the resistancevalue of the resistance Tp3, the potential level of the node B that hasshifted to the high-level side is prevented from decreasing to below thethreshold voltage of the first-stage inverter INV3 of the buffer BUF2 onthe output side after it has once exceeded the threshold voltage.

Contrary to the above, when the level of the input signal at the inputsignal terminal IN changes its level from high to low, operation reverseto the operation described above is performed. Specifically, the Nch MOStransistor Tn2, to the gate of which a signal in opposite phase to theinput signal IN, that is, a signal changing from low to high is applied,starts going ON, allowing a current to start flowing from the node B tothe ground VSSH through the Nch MOS transistor Tn2, and thus ONresistance of the Nch MOS transistor Tn2 gradually decreases. Thisreduces the drain-source voltage of the Nch MOS transistor Tn2 and thuslowers the level of the node B. Roughly simultaneously with this, theNch MOS transistor Tn1, to the gate of which a signal in phase with theinput signal IN is applied, gradually increases its ON resistance. Thisincreases the drain-source voltage of the Nch MOS transistor Tn1, andthe level of the node A starts to rise.

With the shift of the node B to the low level, the gate voltage of thePch MOS transistor Tp1 falls, causing start of ON operation, and thusthe drain voltage of the Pch MOS transistor Tp1, that is, the level ofthe node A rises. The node A shifting to the high-level side was in thelow level before the change of the input signal IN, and the node Bshifting to the low-level side was in the high level before the changeof the input signal IN. Therefore, simultaneously with, or from thestage prior to, the start of the ON operation of the Pch MOS transistorTp1, a current flows from the node B on the high-level side to the nodeA on the low-level side through the resistance (Pch MOS transistor) Tp3,and this speeds up the potential rise at the node A shifting to thehigh-level side.

Thanks to the speedup of the potential rise at the node A shifting tothe high-level side, the gate voltage of the Pch MOS transistor Tp2rises swiftly, allowing the Pch MOS transistor Tp2 to start going OFFearly. Therefore, the supply of the high power-supply voltage VDDHbecomes difficult, and this speeds up the level fall of the node B. Thisresults in shortening the time taken for the level of the node B tobecome below the threshold voltage of the first-stage inverter INV3 ofthe buffer BUF2 operating at a high power-supply voltage, allowing theoutput signal from the output terminal OUT of the buffer BUF2 to becomethe ground voltage VDDL early.

In the level shift circuit of this embodiment shown in FIG. 1, thepotential at the node A or B on the high-level side is a potentialdetermined by the resistance division among the three serially-connectedtransistors (Tp1, Tp3 and Tn2) or (Tp2, Tp3 and Tn1) that are in the ONstate, and will not be the high power-supply voltage VDDH. Therefore, inthe transistor Tp3 additionally supplied, the conventional trouble thata reverse bias of the high power-supply voltage VDDH is applied to itsback gate and drain can be avoided, and thus reliability is wellsecured.

Embodiment 2

A level shift circuit of Embodiment 2 of the present invention will bedescribed.

FIG. 2 shows a configuration of the level shift circuit of Embodiment 2.The level shift circuit shown in FIG. 2 is different from the levelshift circuit of FIG. 1 in that the transistor constituting theresistance was the Pch MOS transistor Tp3 in FIG. 1 but is a Nch MOStransistor Tn3 in this embodiment. Specifically, the Nch MOS transistor(resistance) Tn3 is connected to the node A at its source and to thenode B at its drain, and the gate thereof is connected to thehigh-voltage power supply VDDH, to allow for normally ON operation.

Therefore, in this embodiment, also, the same function and effect asthose in Embodiment 1 can be obtained.

Embodiment 3

A level shift circuit of Embodiment 3 of the present invention will bedescribed.

FIG. 3 shows a configuration of the level shift circuit of Embodiment 3.The level shift circuit shown in FIG. 3, of which output signal is adifferential signal, is different from the level shift circuit of FIG. 1in that a buffer BUF3 is additionally provided on the output side.

The buffer BUF3 on the output side includes two inverters INV5, INV6operating at the high power-supply voltage VDDH and the correspondingground VSSH. The first-stage inverter INV5 is connected to the node A.The outputs of the two buffers BUF2 and BUF3 on the output side areconnected to an output terminal OUTP outputting a signal in phase withthe input signal IN and an output terminal OUTN outputting a signal inopposite phase to the input signal IN, respectively. The outputterminals OUTP and OUTN constitute a pair of differential outputterminals.

In this embodiment, although the placement of the pair of differentialoutput terminals OUTP and OUTN was applied to the level shift circuit ofFIG. 1, this placement is also applicable to the level shift circuit ofFIG. 2.

Embodiment 4

FIG. 4 shows a level shift circuit of Embodiment 4 of the presentinvention.

The level shift circuit shown in FIG. 4 is the same in configuration asthe level shift circuit shown in FIG. 1, except that a Pch MOStransistor Tp4 for connecting the two nodes A and B receives a standbymode signal Stb at its gate as an ON/OFF operation switch signal. In thenormal operation mode in which a high-frequency high-speed signal isinput via the input terminal IN, the standby mode signal (operation modeswitch signal) Stb falls to the low level VSSH, to put the Pch MOStransistor (resistance) Tp4 additionally provided in the normally ONstate. In the standby mode in which a low-frequency low-speed signal isinput via the input terminal IN, the standby mode signal Stb rises tothe high level VDDH, to put the Pch MOS mode transistor (resistance) Tp4in the normally OFF state. The standby mode signal Stb is supplied froman LSI (semiconductor integrated circuit) including the level shiftcircuit of this embodiment.

In this embodiment, therefore, in the standby mode, in which alow-frequency low-speed signal is input via the input terminal IN, nohigh-speed level shift operation is necessary for the level shiftcircuit, but normal speed is enough. In this situation, the standby modesignal Stb of the high level VDDH is input, to put the Pch MOStransistor (resistance) Tp4 in the normally OFF state. In this state,the operation of speeding up the potential rise at the node shifting tothe high level with supply of a current from the node on the high levelside is stopped. Therefore, the level shift circuit performsnormal-speed level shift operation. In this way, in the standby mode,redundant operation as conventionally done is not involved, and thuslower power consumption than in the conventional case can be achieved.

In this embodiment, the standby mode signal Stb was input into the PchMOS transistor (resistance) Tp4. Alternatively, a sleep mode signal andthe like may be used. The level shift circuit of FIG. 1 was modified toobtain the level shift circuit of this embodiment. Naturally, the levelshift circuits of FIG. 2 and FIG. 3 may be modified to obtain the levelshift circuit of this embodiment. In the case using the Nch MOStransistor (resistance) Tn3, the standby mode signal Stb of the lowlevel VSSL may be input in the standby mode.

The level shift circuits of the present invention were described withreference to FIGS. 1 to 4. The present invention also includes asemiconductor integrated circuit having any of such level shiftcircuits, a low power-supply voltage operating circuit and a highpower-supply voltage operating circuit, in which an output signal fromthe low power-supply voltage operating circuit is level-shifted to ahigh power-supply voltage VDDH and the voltage VDDH is output to thehigh power-supply voltage operating circuit.

INDUSTRIAL APPLICABILITY

According to the present invention, with only addition of oneresistance, high-speed level shift operation can be attained while thereliability of the resistance is well secured. Therefore, the presentinvention is useful as a small-size level shift circuit forlevel-shifting a low-voltage signal to a high-voltage signal at highspeed in propagation of a signal between a plurality of circuit sectionshaving different power-supply voltages, and a semiconductor integratedcircuit including such a level shift circuit and the plurality ofcircuit sections.

1. A level shift circuit comprising: first and second P-channeltransistors of which sources are connected to a high-voltage powersupply; and first and second N-channel transistors of which sources aregrounded, wherein complementary input signals in phase with and inopposite phase to an input signal from a low power-supply voltageoperating circuit are respectively inputted to gates of the first andsecond N-channel transistors, a drain of the first N-channel transistoris connected to a drain of the first P-channel transistor and a gate ofthe second P-channel transistor, a drain of the second N-channeltransistor is connected to a drain of the second P-channel transistorand a gate of the first P-channel transistor, the level shift circuitfurther comprises a resistance connecting the drain of the firstN-channel transistor with the drain of the second N-channel transistor,and the drain of the second N-channel transistor serves as an outputterminal to a high power-supply voltage operating circuit.
 2. The levelshift circuit of claim 1, wherein the resistance is constructed of aP-channel transistor, and the P-channel transistor is grounded at itsgate, connected to the drain of the first N-channel transistor at itssource, and connected to the drain of the second N-channel transistor atits drain, to be in the normally ON state.
 3. The level shift circuit ofclaim 1, wherein the resistance is constructed of an N-channeltransistor, and the N-channel transistor is connected to a high-voltagepower supply at its gate, connected to the drain of the first N-channeltransistor at its source, and connected to the drain of the secondN-channel transistor at its drain, to be in the normally ON state. 4.The level shift circuit of claim 1, wherein the resistance isconstructed of a P-channel transistor, and the P-channel transistorreceives an ON/OFF operation switch signal at its gate, connected to thedrain of the first N-channel transistor at its source, and connected tothe drain of the second N-channel transistor at its drain.
 5. The levelshift circuit of claim 1, wherein the resistance is constructed of anN-channel transistor, and the N-channel transistor receives an ON/OFFoperation switch signal at its gate, connected to the drain of the firstN-channel transistor at its source, and connected to the drain of thesecond N-channel transistor at its drain.
 6. The level shift circuit ofclaim 4, wherein the ON/OFF operation switch signal is an operation modeswitch signal received from outside.
 7. The level shift circuit of claim1, wherein the drains of the first and second N-channel transistorsserve as differential output terminals for the high power-supply voltageoperating circuit.
 8. A semiconductor integrated circuit comprising thelevel shift circuit of claim 1.